Semiconductor devices including integrated circuits (IC) operate at increasingly higher frequencies and data rates and at lower voltages. Higher operating frequencies, that is, higher IC switching speeds, mean that voltage response times to the IC must be faster. Lower operating voltages require that allowable voltage variations (ripple) and noise become smaller.
For example, as a microprocessor IC switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or power droop that will exceed the allowable ripple voltage and noise margin; the IC will malfunction. Additionally, as the IC powers up, a slow response time will result in power overshoot.
Consequently, the production of noise in the power and ground (return) lines and the need to supply sufficient current to accommodate faster circuit switching pose an increasingly important problem in semiconductor devices.
Controlling power droop and overshoot within allowable limits, thereby stabilizing power delivery to the IC, is achieved by the use of capacitors placed close enough to the IC to provide or absorb power within the appropriate response time. Lowering noise in the power distribution system is accomplished by lowering impedance.
In conventional circuits, impedance is reduced by the use of additional surface mount capacitors interconnected in parallel and clustered around the IC. Large value capacitors are placed near the power supply, mid-range value capacitors at locations between the IC and the power supply, and small value capacitors very near the IC. This distribution of capacitors is designed to reduce voltage response time as power moves from the power supply to the IC. As frequencies increase and operating voltages continue to drop, increased power must be supplied at faster rates, which requires increasingly lower inductance and impedance levels.
FIG. 1 is an electrical schematic of placement of capacitors with respect to an IC device and the power supply. Shown is a power supply, an IC device and the capacitors 4, 6 and 8, which represent high value, mid-range value and small value capacitors, respectively, used for impedance reduction and minimizing power droop and dampening overshoot as described above.
FIG. 2 is a representative section view in front elevation of a PWB according to the electrical schematic represented by FIG. 1 and shows prior art connections of Surface Mount Technology (SMT) capacitors 50 and 60 (capacitors identified as 8 in FIG. 1) and IC device 40 to the power and ground planes in the substrate of the PWB. IC device 40 is connected to lands 41 by solder filets 44. Lands 41 are connected to plated through hole via pads of vias 90 and 100 by circuit lines 72 and 73. Via pads are shown generically as 82. Via 90 is electrically connected to conductor plane 120 and via 100 is connected to conductor plane 122. Conductor planes 120 and 122 are connected to the power or voltage side of the power supply and to the ground or return side of the power supply. Small value capacitors 50 and 60 are similarly electrically connected to vias and conductor planes 120 and 122 in such a way that they are electrically connected to IC device 40 in parallel. In the case of IC devices placed on modules, interposers, or packages, the large and medium value capacitors may reside on the printed wiring mother board to which the modules, interposers, or packages are attached.
Interconnecting a large number of capacitors in parallel, which is the conventional practice shown in FIG. 1 as conventionally practiced, reduces power system impedance but also requires complex electrical routing. This has the unfavorable consequence of increasing circuit loop inductance, which in turn increases impedance, constrains current flow and in part reduces the benefit of using surface mounted capacitors. As frequencies increase and operating voltages continue to drop, increased power must be supplied at faster rates requiring increasingly lower inductance and impedance levels.
Considerable effort has been expended to minimize impedance. U.S. Pat. No. 5,161,086 to Howard et al. discloses a capacitive printed circuit board having a capacitor laminate (planar capacitor) placed within multiple layers of the board, onto which has been placed a large number of devices, such as integrated circuits. These devices are operatively coupled with the capacitor laminate(s). Howard et al. provides increased capacitive function by employing borrowed or shared capacitance. However, this approach to capacitor placement does not provide high capacitance and does not necessarily improve voltage response. Simply placing the capacitor laminate closer to the IC is not a satisfactory technical solution to provide high capacitance as the total available capacitance may be insufficient to adequately minimize impedance.
U.S. Pat. No. 6,611,419 to Chakravorty discloses that power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate.
U.S. Pat. App. Pub. No. 2006-0138591 to Amey et al. discloses methods for incorporating high capacitance capacitors into the core of a printing wiring board and merely suggests that these may be placed in the build-up layers. However, Amey et al. does not disclose or suggest methods for placing tested and known good capacitors into the build-up layers. Moreover, the Amey et al. methods of forming capacitors do not teach or contemplate testing of capacitors at the foil level since the Amey et al. capacitors are shorted at the foil level. In addition, Amey et al. does not disclose how it is possible to affect yield of the final PWB product by either discarding entire foils with poor capacitor yield or individual capacitors that have tested bad.
Hirata et al. in “Development of Novel Thin Material for Decoupling Capacitors Embedded in PWBs”, Proceedings of the Technical Conference, IPC Printed Circuits Expo, Los Angeles, 2007 disclose forming a metal/insulator/metal (MIM) laminate structure, patterning and etching the top metal layer to form electrodes and cutting the structure into individual, singulated capacitors, 1 mm2 to 100 mm2 in size. These capacitors can be tested and the known good capacitors attached to the printed wiring board using adhesive. The capacitor size and design are not suited to deliver power to an IC, such as a microprocessor, having many power and ground terminals. Hirata et al. cannot suggest the technical solution described herein.
Thus, a current problem is to develop methods of incorporating, that is, placing a plurality of capacitors into the build-up layers of a PWB, each capacitor being “known good” and having a size and a pitch whereby: each placed capacitor lies directly under and within the dimensions of the IC; and each power and ground terminal of the IC, such as a microprocessor, can be directly connected to the power and ground electrode, respectively, of a unique, placed capacitor.
The methods described herein solve this problem by using only known good capacitors to form a plurality of placed capacitors having very small sizes and of a fine pitch that allows all capacitors to lie directly under and within the dimensions of the IC. No combination of Howard et al., Chakravorty, Amey et al. and Hirata et al. or of other references suggests the present solution or constitutes a predictable result. Creating capacitors having these three features—of “known good” quality and of a size and a pitch—allows the incorporation of as many known good, singulated capacitors directly under and within the dimensions of the IC as an IC has power and ground terminals. This has the effective result of providing power to the IC at low impedance and creating a qualifiedly reliable PWB product.